1. Field of the Invention
This invention relates in general to an improved method of manufacturing solar cells that results in an improved solar cells and solar cell arrays, more specifically to manufacturing multiple junction solar cell circuits on a single wafer, and most specifically to manufacturing multiple solar cells in series on a single wafer.
2. Description of the Related Art
Current multi-junction solar cell circuits for space missions employ Ge, GeAs, and/or InP wafer substrates sectioned from single crystal ingots. An alternative method of manufacture of such substrates is to grow the Ge, GeAs, or InP directly on silicon wafers (through a lattice mismatch process) by growing gradient that slowly matches the silicon lattice to the Ge, GeAs, or InP lattice. In order to promote such growth, relatively high temperatures, of between about 425° C. and 900° C., are required, depending upon the chemical compound being grown.
State of the art solar cells are triple junction solar cells, comprising three full junction layers manufactured on single crystal Ge wafers, that require by-pass diodes between each triple junction cell when assembled in series to prevent damage in case of shadowing. After the triple junction solar cells are formed an out-of-plane stress relief loop is arranged between each of the contacts/conductors interconnection on the cells.
In using this technique for manufacture, non-isolated multi-junction solar cells are manufactured on each Ge wafer. The solar cells are subsequently diced into single isolated cells. This is necessary due to the fact that the cells are connected in parallel on the wafer. End user of this technology generally require high voltage arrays resulting in the cells being connected in series, with by-pass diodes. These interconnects (for arranging the cell circuits in series to form a cell array) require a stress-relief loop as well as the diodes placement on or near the cells make arranging multiple cell circuits on a single Ge wafer problematic.
While multi-junction solar cells manufactured using the above described technique have a relatively high efficiency related to commercial, single junction solar cells, several problems related for use in space missions exist.
First, when arranging the cells into a cell array, a large surface area is required due to the economics (cost) of handling parts on a production line. Second, due to the potentially large differential in voltage across an array between cells, there is a tendency for arcing to occur when the arrays are exposed to a space environment. Third, each wafer, having only one solar cell circuit, can only produce voltages of about 2 volts.
Therefore, it is desired to provide a solar cell circuit using a manufacturing technique that will allow for multiple multi-junction circuits to be placed on one lightweight silicon wafer, producing a high voltage, and obviating the potential for arcing across a solar cell circuit array.